Advanced Topics in Computer Engineering
Reading List
| Date | Paper |
| 1/7 | Intro Lecture |
| 1/9 | Foundation Lecture |
| 1/11 | Balfour et al., “An Energy-Efficient Processor Architecture for Embedded Systems,” CAL 2008 Hameed et al., “Understanding Sources of Inefficiency in General-Purpose Chips,” ISCA 2010 |
| 1/14 | Shaw et al., “Anton 2: Raising the Bar for Performance and Programmability in a Special-Purpose Molecular Dynamics Supercomputer,” SC 2014 |
| 1/16 | Ozdal et al., “Energy Efficient Architecture for Graph Analytics Accelerators,” ISCA 2016 |
| 1/18 | Eyerman et al., “Many-Core Graph Workload Analysis,” SC 2018 |
| 1/21 | Holiday |
| 1/23 | Ahn et al., “A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,” ISCA 2015 |
| 1/25 | Dysart et al., “Highly Scalable Near Memory Processing with Migrating Threads on the Emu System Architecture,” IA^3 2016 Rolinger et al., “Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture,” IA^3 2018 |
| 1/28 |
Shao et al., "Aladdin: a Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures," ISCA 2014 Guest: Sophia Shao |
| 1/30 |
Magaki et al., "ASIC Clouds: Specializing the Datacenter," ISCA 2016 Guest: Heiner Litz |
| 2/1 | Chen et al., “DaDianNao: A Machine-Learning Supercomputer,” MICRO 2014 |
| 2/4 | Han et al., “EIE: Efficient Inference Engine on Compressed Deep Neural Network,” ISCA 2016 |
| 2/6 | Chen et al., “Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks,” ISCA 2016 |
| 2/8 |
Jouppi et al., “In-Datacenter Performance Analysis of a Tensor Processing Unit,” ISCA 2017 Guest: David Patterson |
| 2/11 | Goulding-Hotta et al., “The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future,” IEEE Micro 2011 |
| 2/13 | Huang et al., “Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling,” FPGA 2017 |
| 2/15 | Turakhia et al., “Darwin: A Genomics Co-processor Provides up to 15,000X Acceleration on Long Read Assembly,” ASPLOS 2018 |
| 2/18 | Holiday |
| 2/20 | Putnam et al., “A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services,” ISCA 2014 |
| 2/22 | Fowers et al., “A Configurable Cloud-Scale DNN Processor for Real-Time AI,” ISCA 2018 |
| 2/25 | Prabhakar et al., “Plasticine: A Reconfigurable Architecture For Parallel Paterns,” ISCA 2017 |
| 2/27 | Nowatzki et al., “Stream-Dataflow Acceleration,” ISCA 2017 |
| 3/1 | Fuchs et al., "The Accelerator Wall: Limits of Chip Specialization," HPCA 2019 |
| 3/4 | Khailany et al., “Imagine: media processing with streams,” IEEE Micro 2001 |
| 3/6 | Ahn et al., “Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs,” CAL 2009 McSherry et al., “Scalability! But at what COST?,” HotOS 2015 |
| 3/8 | Wu et al., “Q100: The Architecture and Design of a Database Processing Unit,” ASPLOS 2014 |
| 3/11 | Project Presentations |
| 3/13 | Project Presentations |
| 3/15 | Project Presentations |
UCSC Library Instructions for off-campus access
Additional Reading
| Gordon Moore, "Cramming More Components onto Integrated Circuits," Electronics 1965 |
| Esmaeilzadeh et al., "Dark Silicon and the End of Multicore Scaling," ISCA 2011 |
| Ho et al., "The Future of Wires," IEEE 2001 |
| Asanovic et al., "The Landscape of Parallel Computing Research: A View from Berkeley", TR 2006 |
| Shao et al., "Research Infrastructures for Hardware Accelerators," M&C 2015 |
| Shao et al., "ISA-Independent Workload Characterization and Its Implications for Specialized Architectures," ISPASS 2013 |
| Dally et al., "Efficient Embedded Computing," IEEE Computer 2008 |
| Shaw et al., "Anton, A Special-Purpose Machine for Molecular Dynamics Simulation," ISCA 2007 |
| Ham et al., "Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics," MICRO 2016 |
| Beamer et al., "Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server," IISWC 2015 |
| Taylor, "Bitcoin and The Age of Bespoke Silicon," CASES 2013 |
| Taylor, "The Evolution of Bitcoin Hardware," Computer 2017 |
| Khazraee et al., "Moonwalk: NRE Optimization in ASIC Clouds or, Accelerators Will Use Old Silicon," ASPLOS 2017 |
| Govindaraju et al., "DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing," IEEE Micro 2012 |
| Caulfield et al., "A Cloud-Scale Acceleration Architecture," MICRO 2016 |