Programmable Hardware Accelerators (Winter 2019)

When: MWF 02:40PM-03:45PM (165 Baskin Engineering)

Instructor: Scott Beamer (

Office Hours: MW 4-5 PM (E2-229) or by appointment

This graduate course will explore the current research and industrial landscape of programmable hardware accelerators. By specializing for a target domain, hardware accelerators can deliver outstanding efficiency improvements which makes them a promising way to cope with Moore's Law slowing down. This course will cover not only accelerators from a wide range of domains, but also foundational concepts to understand how to evaluate acceleration opportunities. Example accelerators include: deep learning (e.g. TPU), reconfigurable logic (FPGA and CGRA), bioinformatics, and graph processing. After completing this course, students will be able to analyze a given a target application and recommend an accelerator for it. The course will consist primarily of paper readings, paper discussions, student presentations, and course projects.

Prerequisites: CMPE 110 or equivalent (undergraduate computer architecture)

Canvas (for submitting work)

Piazza (for discussion)